The Extended Generalized Shuffle (EGS) class of networks permits very flexible system design while yielding low blocking probabilities and high degrees of fault tolerance. Known optical EGS network designs, for example, the photonic system disclosed in the Cloonan et al. U.S. application Ser. No. 07/349,008 now U.S. Pat. No. 5,023,864 issued Jun. 11, 1991 incorporated by reference herein, and in the published European patent application 90304731.4, use three-dimensional interconnections between two-dimensional arrays of optical logic devices, such as symmetric self electro-optic effect devices (S-SEEDs). These optical logic devices can be operated as AND, OR, NAND, and NOR gates, as well as S-R latches. The optical interconnections between the devices on consecutive arrays are provided by bulk, free space optical elements, such as lenses, beam-splitters, and mirrored gratings. It has been shown that these passive optical elements can be used to provide crossover interconnections between stages of nodes. The known optical EGS designs have limitations due to their reliance on spatial light modulators (SLMs) to effect network control. A SLM is an array of windows (or pixels) that can be made transparent or opaque based on the electronic control signals that are directed to it. In the known optical EGS designs, path hunt processing is performed in an external electronic centralized controller and the results of path hunt processing are transmitted to the optical switching nodes within the network (FIG. 21). The transformation of the electronic control signals in the centralized controller into the optical control signals within the network is performed by the SLMs. Unfortunately, presently available SLM technologies have relatively slow switching times (on the order of microsecond switching). Some of the available SLMs are also inefficient in terms of their output power to input power ratios. Slow switching times make high-speed time-multiplexed switching (TMS) operations (shown in FIG. 22) impractical, and inefficient power utilization limits the achievable system data rates. In addition, the use of SLMs complicates the optical hardware and the opto-mechanics required in the known designs. It is clear, therefore that an optical EGS network that does not require the use of SLMs for network control would have many benefits.
In an optical implementation of a self-routing Starlite packet switch described in A. Huang and S. Knauer, "Starlite: A Wideband Digital Switch," GlobeCom '84, (IEEE 84CH2064-4) (Nov. 1984), Vol. 1, p. 121, network control is accomplished without the use of SLMs by distributing the path hunt processing operations within small processors attached to each of the switching nodes within the Starlite network, and prepending routing information to the transmitted data so that routing information is made available to each switching node that receives the data (FIG. 23). Although each of the distributed processors is much simpler than the centralized controller used in the known optical EGS designs, the inclusion of a processor within each node complicates the hardware requirements for a single node substantially. In fact, whereas a single node in the optical EGS network requires at most four S-SEEDs, a comparable node in the optical Starlite network requires as many as 128 S-SEEDs. Although the operation of a large number of S-SEEDs may become practical in the future, this increase in hardware cost is not presently justified by the benefits associated with the use of optics for network interconnections. As a result, a need exists for a cost-effective optical switching architecture that is not burdened by the operational limitations of present-day SLMs.
U.S. Pat. No. 4,494,230 issued to J. S. Turner on Jan. 15, 1985, discloses an electronic fast packet switching system employing a banyan switching network of 4.times.4 switching nodes to interconnect a plurality of trunk controllers connected to the network inlets and outlets. Each trunk controller stores information to perform logical address to physical address translation once a virtual circuit call has been set up through the system. Before transmitting a packet through the banyan network, an originating trunk controller prepends a physical address including bits usable by the individual 4.times.4 nodes to route the packet to the proper destination trunk controller--i.e., once the physical address is prepended, the packet is self-routing. However, the network includes packet buffering, e.g., each node input buffers one packet. Since there is no a priori determination that a particular path through the network is free at the time the packet is transmitted, it is likely that a given packet will be buffered many times as it traverses the network. This is a significant drawback in terms of delay and overall network performance in many applications.